Journals :

1. H. V. Ravish Aradhya, Dr. K. N. Muralidhara & Praveen Kumar BV,"Design of Low power arithmetic unit based on reversible logic", International Journals of VLSI & Signal Processing Application, March 2011,pp 30-38
2. H. V. Ravish Aradhya, Dr. K. N. Muralidhara & Praveen Kumar BV, "Design of Control unit for Low Power ALU Using Reversible Logic", International Journal of Scientific and Engineering Research, France, Volume 2, Issue 7, ISSN 2229-5518, Sep-2011.
   
   
   

International Conference:

1. H. V. Ravish Aradhya, Dr. K. N. Muralidhara, & Swetha.V “Practical Aspects Power Verification & Automation” in International Conference on Sensors, security, software& Intelligent systems(ISSSIS); CIT, Coimbatore, INDIA during 08.01.2009 To 10.01.2009
2. H. V. Ravish Aradhya,Dr. K. N. Muralidhara, & Prasad P. Kamat “Multi Core ALU – a low power approach” in International Conference on 3CI; RVCE, Bangalore-59, INDIA during 23.11.2007 to 25.11.2007
3. H. V. Ravish Aradhya, Dr. K. N. Muralidhara, & Mahesh K, "Design and Implementation of an Advanced External Interrupt Controller Unit [EICU] on Cortex-R4 Processor", in International Conference; MIT, Manipal, INDIA , to be held in Dec-2010 [SDC 487].
4. Design of Control unit for Low Power AU Using Reversible Logic -IEEE sponsored International Conference on Communication technology and System design (ICCTSD-2011), AIT, Coimbatore, India., from 07.12.2011 to 09.12.2011.
   
   

National Conference:

1. H. V. Ravish Aradhya, Dr. K. N. Muralidhara, & Jeevan Kumar. U “Estimation of Iteration Bound For DSP Algorithms Using LPM Method” in National conference on VLSI and Multimedia communication (NCVM-09) at RVCE, Bangalore-59 during 23.10.09 to 24.10.09
2. H. V. Ravish Aradhya, Dr. K. N. Muralidhara, & Sunitha.S” Practical Aspects Of Boundary Scan “ in National conference on recent trends in communication, electronics and information technology at CMRIT, Bangalore-37 during 14.05.2009 to 15.05.2009
3. H. V. Ravish Aradhya, Dr. K. N. Muralidhara and G. Sunil Kumar Reddy” ASIC Implementation of Systolic Array Architecture for Full Search Block Matching Algorithm” in National conference on Recent Trends in Communication, Electronics and Information Technology at CMRIT, Bangalore-37 during 14.05.2009 to 15.05.2009
4. H. V. Ravish Aradhy,Dr. K. N. Muralidhara, & Sunitha.S “Square FIFO for data transfer between unrelated clock domains” in National conference on recent trends in soft computing at New Horizon CE, Bangalore-87 during 24.04.2009 to 25.04.2009
   
5. H. V. Ravish Aradhya, Dr. K. N. Muralidhara, & Jeevan Kumar. U “Iteration bound of DSP chips” in National conference on information technology & CAD tool for computing at Bangalore Institute of technology, Bangalore-04 during 30.03.2009 to 31.03.2009
6. H. V. Ravish Aradhya, Dr. K. N. Muralidhara, & Swetha.V “Practical aspects of FEV using Cadence LEC” National level technical paper meet in Sambhram Institute of technology, Bangalore-97 during 04.04.2008 to 05.04.2008
7. H V Ravish Aradhya," CAD tool for computing iteration bound DSP chips", National conference on Information Technology; Bangalore Institute of technology, Bangalore-01, INDIA, March 2009
8. H V Ravish Aradhya," Design and Implementation of an optimized systolic array architecture for FSBMA for real time applications", CMRIT, Bangalore, INDIA, March 2009
   
   

Book Publications:

1. "Basic Electronics- the Device principles and circuits ", to be published in June 2011, Mc- GrawHill (I) publications.
2. "Digital Design, 4th Edn, "Pearson Education (I) publications 2008(Adaptation).
3. "Digital Design, 3rd Edn, "Pearson Education (I) publications 2006(Adaptation).
4. "Electronics Devices & circuits theory", 10th Edn, "Pearson Education (I) publications 2008(Adaptation).
5. "Electronics Devices & circuits theory", 9th Edn, Pearson Education (India), 2006(Adaptation to Indian University requirements).
   
   

Awards:

1. Recipient of “Best Teacher Award” from Carrier Launcher (India), Bangalore, May 2006.