Journals:

1. H V Ravish Aradhya, Dr. K. N Muralidhara, "Design, Optimization and Synthesis of Efficient Reversible Logic Binary Decoder," International Journal of Computer Applications (IJCA), New York, USA, ISSN- 0975-8887, May-2012. (Paper Reference ID: pxc3879354).
2. H V Ravish Aradhya, Dr. K. N Muralidhara, "Improved Performance, Reversible Logic BCD Adder/Subtractor suitable for Nanotechnology applications," IEEE –Journal of VLSI systems, USA, submitted Mar-2012. ---Under review
3. H V Ravish Aradhya, Dr. K. N Muralidhara, "Simulation and Synthesis of Combinational Shifter using Reversible Gates", International Journal of Computer Applications, USA, Volume 40, Issue 16, ISSN 0975-8887, Apr-2012.
4. H V Ravish Aradhya, Dr. K. N Muralidhara, "Design Optimization of Reversible Logic Universal Barrel Shifter for Low Power Applications", International Journal of Computer Applications, New York, USA, Volume 40, Issue 15, ISSN 0975-8887, Feb-2012.
5. H V Ravish Aradhya, Dr. K. N Muralidhara, "Design of Control unit for Low Power ALU Using Reversible Logic", International Journal of Scientific and Engineering Research, France, Volume 2, Issue 7, ISSN 2229-5518, Sep-2011.
6. H V Ravish Aradhya, Dr. K. N Muralidhara, G Mithun Kumar, "A Novel assertion based Methodology to verify mixed signal SOC designs in Digital and Mixed signal verification flow", International Journal of Engineering Science and Technology (IJEST), ISSN: 0975–5462, Vol. No. 3, Issue No. 6, June 2011, pp.4721-4727, Jun-2011.
7. H V Ravish Aradhya, Dr. K. N Muralidhara, G Mithun Kumar, "Modelling of complex analog circuits with assertions and automatic processing of Waveforms", International Journal of Advanced Engineering Sciences and Technologies (IJAEST), Vol. No. 6, Issue No. 2, 220 – 223, ISSN: 2230-7818, May-2011.
8. H V Ravish Aradhya, Dr. K. N Muralidhara, "Design of Low Power Arithmetic Unit based on Reversible Logic", International Journal of VLSI and Signal Processing Applications, Vol. 1, Issue 1(30- 38), ISSN: 2231-3575, Apr-2011.

International Conferences:

1. H. V. Ravish Aradhya, Dr. K. N. Muralidhara, "Design, Optimization and Synthesis of Efficient Reversible Logic Binary Encoder," International Conference on Recent Trends in Computer Science and Engineering (ICRTCSE-2012), Apollo College of engineering, Kanchipuram, TN, India.
2. H. V. Ravish Aradhya, Dr. K. N. Muralidhara, and Malleswara Rao, "FPGA implementation of IEEE-754,single precision floating point arithmetic," International Conference on Recent Trends in Computer Science and Engineering (ICRTCSE-2012), Apollo College of engineering, Kanchipuram, TN, India.
3. H. V. Ravish Aradhya, Dr. K. N. Muralidhara, "Design of Control unit for Low Power AU Using Reversible Logic," IEEE sponsored International Conference on Communication technology and System design (ICCTSD-2011), AIT, Coimbatore, India., from 07.12.2011 to 09.12. 2011.
4. H. V. Ravish Aradhya, Dr. K. N. Muralidhara, & Mahesh K, "Design and Implementation of an Advanced External Interrupt Controller Unit [EICU] on Cortex-R4 Processor," International Conference on System Dynamics and Control (ICSDC-10); MIT, Manipal, INDIA , 19-22, Aug-2010.
5. H. V. Ravish Aradhya, Dr. K. N. Muralidhara, & Swetha.V "Practical Aspects Power Verification & Automation," International Conference on Sensors, security, software& Intelligent systems(ISSSIS-09), CIT, Coimbatore, INDIA, 08-10, Jan 2009.
6. H. V. Ravish Aradhya, Dr. K. N. Muralidhara, & Prasad P. Kamat, "Multi Core ALU – a low power approach," International Conference on 3CI; RVCE, Bangalore-59, INDIA, 23-25 Nov, 2007.

National Conferences:

1. H. V. Ravish Aradhya, Dr. K. N. Muralidhara, and Chinmaye R, "Design and Optimization of Reversible Logic Decoder For Low Power Applications", National conference on advanced VLSI and embedded technology (NCAVET-2012), New Delhi, during 28-29, Feb-2012.
2. H. V. Ravish Aradhya, Dr. K. N. Muralidhara, andMadan H. R, "CMOS Realization of Reversible BCD Adder",National conference on Recent Trends in Communication Technology, Vol. no. 01, pp. 227 – 233, during 13.01.2012.
3. H. V. Ravish Aradhya, Dr. K. N. Muralidhara, and Madan H. R, "CMOS implementation of reversible comparators", National conference on Recent Trends in Communication Technology, Vol. no. 01, pp. 227 – 233, during 13.01.2012.
4. H. V. Ravish Aradhya, Dr. K. N. Muralidhara, and Madan H. R, "Design and Performance Analysis of 6T SRAM for Different Scaled Technologies", National conference on Recent Trends in Communication Technology, Vol. no. 01, pp. 227 – 233, during 13.01.2012.
5. H. V. Ravish Aradhya, Dr. K. N. Muralidhara, and Madan H. R, "Comparative Study of logic circuits based on MOSFET and FinFET under 32 nm process technology", National conference on Recent Trends in Communication Technology, Vol. no. 01, pp. 227 – 233, during 13.01.2012.
6. H. V. Ravish Aradhya, Dr. K. N. Muralidhara, and Madan H. R, "Comparative Study of DRAM for various CMOS process technology", National conference on Recent Trends in Communication Technology, Vol. no. 01, pp. 227 – 233, during 13.01.2012.
7. H. V. Ravish Aradhya, Dr. K. N. Muralidhara, andSandeep V, "SPI Interface and Physical Layer of Low Energy Bluetooth",National Level Conference on Computers, Communication and Controls (N4C-11), R. V. College of Engineering, Bangalore, during 29.04.2010 to 30.04.2010.
8. H. V. Ravish Aradhy,Dr. K. N. Muralidhara, and Sandeep V, "Low Energy Bluetooth: An Evolution in Short Range Wireless Communication",National Level Technical Symposium TECHNISIUM'11, Siddaganga Institute of Technology (SIT), Tumkur, during 09.04.2011 to 10.04.2011.
9. H. V. Ravish Aradhya, Dr. K. N. Muralidhara, andJeevan Kumar. U, "Estimation of Iteration Bound For DSP Algorithms Using LPM Method", National conference on VLSI and Multimedia communication (NCVM-09), RVCE, Bangalore-59 during 23.10.09 to 24.10.09
10. H. V. Ravish Aradhya, Dr. K. N. Muralidhara and Mahesh K, "Design and implementation of an advanced external interrupt controller unit [AEICU] on cortex-r4 processor", National Level Conference on Computers, Communication and Controls (N4C-11), R. V. College of Engineering, Bangalore, during 29.04.2010 to 30.04.2010.
11. H. V. Ravish Aradhya, Dr. K. N. Muralidhara and Rohith Kumar C, "Design and implementation of Wireless fire surveillance system", National Level Conference on Computers, Communication and Controls (N4C-11), R. V. College of Engineering, Bangalore, during 29.04.2010 to 30.04.2010.
12. H. V. Ravish Aradhya, Dr. K. N. Muralidhara, andSunitha.S, "Practical Aspects of Boundary Scanand applications beyond interconnect test", National conference on recent trends in communication, electronics and information technology (NCRTCEIT-09), CMRIT, Bangalore-37 during 14.05.2009 to 15.05.2009.
13. H V Ravish Aradhya, Dr. K. N. Muralidhara and G. Sunil Kumar Reddy," Design and Implementation of an optimized systolic array architecture for FSBMA for real time applications", National conference on recent trends in communication, electronics and information technology (NCRTCEIT-09), CMRIT, Bangalore-37 during 14.05.2009 to 15.05.2009.
14. H. V. Ravish Aradhy,Dr. K. N. Muralidhara, and Sunitha.S, "Square FIFO for data transfer between unrelated clock domains" in National conference on recent trends in soft computing (NCRTSC-09), New Horizon CE, Bangalore-87 during 24.04.2009 to 25.04.2009.
15. H. V. Ravish Aradhya, Dr. K. N. Muralidhara and G. Sunil Kumar Reddy, "ASIC Implementation of Systolic Array Architecture for Full Search Block Matching Algorithm", National conference on Recent Trends in Communication, Electronics and Information Technology(NCRTCEIT-09), CMRIT, Bangalore-37 during 14.05.2009 to 15.05.2009.
16. H V Ravish Aradhya," CAD tool for computing iteration bound of DSP chips", National conference on Information Technology (NCIT-09) Bangalore Institute of technology, Bangalore-01, INDIA, March 2009.
17. H. V. Ravish Aradhya, Dr. K. N. Muralidhara, andSwetha.V, "Practical aspects of FEV using Cadence LEC", National level technical paper meet (NLTPM-08),Sambhram Institute of technology, Bangalore-97 during 04.04.2008 to 05.04.2008.

Books:

1. Ravish Aradhya H. V., "Electronic Principles", 1st Edition, McGraw-Hill (India) 2010, MOU signed and to be released in Dec-2012, ISBN-To be published
2. Moris M. Mano, "Logic Design", 4th Edition, ISBN-978-81-317-1450-8, Pearson Education (India), Adapted, 2007 (Adapted to Indian University requirements).
3. Moris M. Mano, "Logic Design", 3rd Edition, ISBN-978-81-317-6280-6, Pearson Education (India), Adapted, 2006 (Adapted to Indian University requirements).
4. L. Nashelsky and R. Boylestead, "Electronics Devices & circuits theory", 10th Edition, ISBN-978-81-317-2700-3, Pearson Education (India), Adapted, 2009 (Adapted to Indian University requirements).
5. L. Nashelsky and R. Boylestead, "Electronics Devices & circuits theory", 9th Edition, ISBN-978-81-317-0314-2, Pearson Education (India), Adapted, 2007 (Adapted to Indian University requirements).
6. Bhaskara -"Switching theory and logic design", ISBN-978-12-590-0442-1, McGraw-Hill (India),Reviewed, 2011.
7. Bhaskara -"VLSI design", ISBN-NA, McGraw-Hill (India), Reviewed, 2011.
   

Awards:

1. Recipient of “Best Teacher Award” from Carrier Launcher (India), Bangalore, May 2006.